1. Field of the Invention
The present invention relates to a manufacturing method of a laminated substrate by laminating a first semiconductor substrate to a second semiconductor substrate via an oxide film. More particularly, the present invention relates to a manufacturing method of an SOI (Silicon On Insulator) substrate in using a silicon substrate as the semiconductor substrate for example, and a laminated substrate manufactured by the method.
2. Description of the Related Art
Conventionally, as manufacturing methods of an SOI substrate, there are known a manufacturing method of an SOI substrate utilizing a lamination method of laminating a first semiconductor substrate, that is to be an SOI layer, to a second semiconductor substrate, that is to be a supporting substrate, via an oxide film, and a manufacturing method of the SOI substrate utilizing an SIMOX (Separation by IMplanted OXygen) method of forming the oxide film within a silicon substrate by ion implantation of oxygen in high concentration into the silicon substrate. As compared with the manufacturing method of the SOI substrate utilizing the SIMOX method, however, the manufacturing method of the SOI substrate utilizing the lamination method requires to use two substrates, i.e., the first and second silicon substrates, and the method may cause a lamination defect, such as a void (FIG. 4) or a blister (FIG. 5), being generated due to particles, organic substances, or the like adhered to the substrate surface in a lamination step, or degradation in the electrical property of a device due to the contamination of the substrate with a dopant or a metal, which lead to the difficulty in controlling the yield of the laminated substrate.
In order to eliminate these problems, the technique with regard to the environment, i.e., a clean room, where the lamination of the aforementioned two substrates is carried out has been improved, and an automated lamination apparatus, such as a clean robot, without the need of human intervention has been introduced, enabling the yield of the SOI substrate utilizing the lamination method to be improved substantially. In this regard, methods of improving the above-described technique with regard to the clean room include methods of: providing a dust-proof air filter in a vent hole to prevent the particles or gaseous contaminants in the air from penetrating into the clean room; utilizing a substrate case which can be handled without introducing the atmosphere external to the apparatus in handling the substrate into the apparatus; decreasing the generation of dust by reducing the dust generation of respective members in the clean room; preventing the static buildup on the substrate by means of an ionizer which ionizes the air in the clean room to neutralize charges on the substrate surface with ions of the reversed polarity; or washing the substrate with a chemical solution added with a surfactant.
Meanwhile, there has been developed a thin film SOI substrate with the SOI layer of 0.1 μm or less in thickness, in order to speed up a circuit by reducing the junction capacitance (electric capacity) between a source/drain and the substrate, to reduce the power consumption of the circuit by reducing a leak current, or to enhance the integration by miniaturization.
In this thin film Sol substrate, there is a problem where the particles with a size on the order of 0.1 μm, which has not been an issue previously, cause the lamination defect.
In order to eliminate the problem, there are disclosed the manufacturing method of the laminated semiconductor substrate in which the carbon concentration in the atmosphere in laminating the two semiconductor substrates is set to 100 ppt (part per trillion) or less (for example, see Patent Document 1), or the manufacturing method of a laminated wafer using a hydrogen ion implantation separation method in which the carbon concentration on the lamination surface of the two substrates is set to 3×1014 atoms/cm2 or less (for example, see Patent Document 2). In the manufacturing method of the laminated semiconductor substrate in the aforementioned Patent Document 1, there is described that, by controlling the carbon concentration in the lamination atmosphere, particularly of the principal surface of the substrate upon lamination, to constrain the carbon concentration on the lamination surface of the two substrates, it achieves high bonding strength even after a lamination heat treatment and the separation does not occur at the lamination surface. Additionally, in the manufacturing method of the laminated wafer in Patent Document 2, there is described that, by setting the carbon concentration on the lamination surface, as an index of a bonding failure of the laminated substrate and organic substance contamination of the lamination surface, to 3×1014 atoms/cm2 or less, it can prevent generation of a separation failure in which the substrates do not separate at an ion implantation area after a separation heat treatment or of the bonding failure in which the whole or a portion of the lamination surface of the two substrates separates, as well as generation of the void when the subsequent bonding heat treatment at a high temperature is carried out.
[Patent Document 1] Japanese Patent No. 3142206 (claim 1, paragraphs [0005] and [0009])
[Patent Document 2] Japanese Unexamined Patent Publication (Kokai) No. 2000-30992 (claim 2, paragraphs [0009], [0010], and [0011])